Improvements in PHY Low Power Analysis and Verification

Abstract

The voltages and currents within a chip’s logic circuitry have been on a downward trajectory along with node sizes, but the dimensions of the outside world have not changed in the same manner. Wires outside the package are hundreds of times longer, and they have much higher capacitance and resistance. Inside the chip, processing has become faster, and that depends on getting enough memory throughput—or access to the raw data required—which in turn means that the external interfaces must operate at an ever-faster rate.Pushing data at ever-faster rates through boards and systems consumes increasing amounts of power, but the power budget for chips has not been increasing.PHYs need high drive capability and often contain circuits that try to compensate for the bad things that happen between the chip and the other end. That means they are also power hungry.A third to a half of the total power is consumed just for the PHYs. This thesis report aims at providing the current improvements in the area of efficient low power design.As the technology size shrinks it brings a lot of complexity in the analysis and verification of the design process. The use of innovative design techniques to overcome leakage has created new challenges for verification that demand a creative response.No individual tool can sufficiently verify all the tricky issues engendered by today’s low-power techniques.The report also deals with test case where a raw design is taken from staic verification and power exploration stage to the sign off stage employing the power checks and strategies defined to bring out a clean power efficient design.