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http://10.1.7.192:80/jspui/handle/123456789/8859
Title: | Configurable RTL Generation Using Automation |
Authors: | Rathore, Ritu |
Keywords: | EC 2016 Project Report Project Report 2016 EC Project Report EC (VLSI) VLSI VLSI 2016 16MEC 16MECV 16MECV20 |
Issue Date: | 1-Jun-2018 |
Publisher: | Institute of Technology |
Series/Report no.: | 16MECV20; |
Abstract: | The integration of IP in a subsystem continues to be a key challenge in SoC development. Yesterday it comprised of integrating internal known IPs, but today the complexity has been increased because of unfamiliar external IP integration. We wish it to be like plug and play solution to build the subsystem and deliver it within weeks, as it minimizes or eliminates the need of RTL modification to meet SoC requirements and it is an obvious need considering time to market. An efficient solution is needed so IP provider’s main focus should not shift from IP development/enhancement to IP delivery and the integration teams will have a library of compiled IPs which they can call and integrate on demand. The adoption and integration of commercial IP reduces the cost and time-to-market of SoCs while dramatically raising the bar of innovation versus the competition. As IP adoption and reuse become more mainstream in SoC realization, IP integration is increasingly seen as a key challenge and a growing contributor to the overall cost of SoC development. The poor adoption of standards and methodologies for IP integration is making efficient and reusable integration more difficult. A solution is needed that provides a balance between abstraction and automation while enabling IP configurability, IP quality, and predictable IP integration. This thesis covers the configurable approach for both IP level as well as subsystem level.This approach provides the platform for homogeneous & transparent integration of any mix of configurable/nonconfigurable IPs. It greatly reduces the turnaround time. Here the in-house solution used is not industry standard. Key benefits of having standardized IP database is interoperability. In case of SoC design it involves the sharing of data or processes across different organizations and disciplines.So, future scope is to come up with more efficient solution, which can replace the current solution with a standardized solution. |
URI: | http://10.1.7.192:80/jspui/handle/123456789/8859 |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
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16MECV20.pdf | 16MECV20 | 1.6 MB | Adobe PDF | ![]() View/Open |
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