Accelerating the Speed of Integrating IPs into SoC

Abstract

System-on-Chip (SoC) is an integrated circuit that contains many electronics components become a single system. It has to ensure every single components and the whole integrated system to work properly. As the process technology is advancing, designs are becoming more complex and more feature rich, thus increasing the cost of development. Also, a huge effort is required to meet the time-to-market needs of SoCs without compromising the product quality. SoCs generally, integrate a large portion of pre-designed and pre-tested IPs. Due to critical time to market, SoC integrator try to increases speed of the integration of IP in to SOC.The three stages which consumes the significant amount of time in above process are Compilation, Elaboration and Simulation. In functional design verification, there are a number of test scenarios to be validated using a simulator. For large designs this could mean the consumption of many resources (time and machines). To improve resource usage, common stages of the simulation could be combined to run only once, example compilation and elaboration of the design. Then each test case could utilize this output to validate the specific objective. IP reuse methodology and integration with third party core-tools helps to meet the time-to-market. This thesis discuss about the methodologies such as Save and Restore and Fine-Grained Parallelism which can significantly reduces the SoC build . The thesis will focus more on the two levels gatekeeper (GK) concept used to reduce the SoC turn in time.The results with respect to the cost and time saving for debug efforts with this methodologies will be compared with the previously used one level gatekeeper (GK) methodology.