ASIC Design and Implementation of 4 Bit DAC

Abstract

This thesis briefly gives us the design and realization of a 250MSP/s 4-bit digital-to-analog converter (DAC) for the ADC which are used in Microwave Remote Sensing Satellites.The resolution of the DAC is 4 bits. The design implemented using PMOS Switch and NMOS Switch where the digital input 0000-1111 (For n bit 2n inputs is considered) with 3.3 V supply in CMOS 180 nm technology. Cadence Virtuoso Analog Design Environment is used for implement the analog circuits, and the architecture is a single core. The binary resistor DAC includes building blocks such as resistor, current switches, and Folded Cascode Op-Amplifier circuit.The binary currentsteering DAC includes building blocks such as current sources, current switches, and Folded Cascode Op-Amplifier circuit.The current sources are designed with the help of PMOS. Step ramp (Staircase) output .Various configuration of switches such as NMOS switch, PMOS Switch, cascaded PMOS and NMOS Switches. The linearity parameters Integral nonliterary (INL) and Differential nonlinearity (DNL) has been checked in the output graph. In the design of Current Steering DAC using the above switches one encounters INL/DNL error and that’s why a capacitve DAC configuration has been used to generate a step ramp(staircase) output. It replaces the current source with capacitors. This DAC uses a total capacitance of 2nCo for converting an n bit digital input into its equivalent analog value, where Co is the unit capacitance value. This configuration improves thus INL/DNL in the output graph. This architecture is verified in simulation and a layout is made doing pre-layout and post layout analysis using Cadence 180nm technology.