Implementation of Cortex A Series Processor On FinFET Technology

Abstract

Perform an optimized implementation of Cortex-A Series CPU in terms of PPA (Performance, Power and Area) on new technology node was challenging in terms of obtaining optimal PPA in each given deadline. The problem statement was to achieve high performance configuration of CPU at given worst corner and to optimize the dynamic and leakage power. For achieving this target, many implementation trials were done. The aim was to achieve high performance at given corner and then to reduce the area by maintaining the same performance and finally to reduce the leakage and dynamic power. All the targets were achieved in terms of optimal PPA in the end of project. Main challenges were faced during reporting of dynamic power and then to optimize it. Also, to decide which track (standard cell height) is better in terms of performance, power and area for a technology node, we perform SHMOO Analysis (standard cell architecture benchmarking). After running SHMOO on different tracks, we decide which track will be better for high performance, mid-range frequency targets and low power targets. Also to implement same design on two tools i.e. Cadence and Synopsys having same specification is difficult.