Implementation Of 32 Bit SPARC Processor On 180nm CMOS Process

Abstract

As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000 logic gates to over 100 million. Modern System on Chip(SoC) often include entire microprocessors, memory blocks including RAM, ROM and other large building blocks. In this project, efforts are made to develop an ASIC using SPARC processor. Over the years SPARC processor is implemented by several different industrial organization and has enabled various space misssions. A payload controller is going to be developed using SPARC V8 processor core with additional peripherals as the On Board Controller(OBC). Processor is connected with various custom peripherals using AHB/APB bus. The AMBA Advanced High-performance Bus (AHB) is a multi-master bus suitable to interconnect units that are capable of high data rates. The AMBA Advanced Peripheral Bus (APB) is a single-master bus suitable to interconnect units of low complexity which require only low data rates. An APB bus is interfaced with an AHB bus by means of a single AHB slave through the AHB/APB bridge. Various peripherals like TSRG (Time Signal Regenerator), Watchdog Timer, SSR (Serial Synchronous Receiver), SST (Serial Synchronous Transmitter), CRM (Clock Reset Module), ADI (Auxiliary Data Interface), SPI(Serial Peripheral Interface), MIL1553-STD-1553B are connected with the processor using AHB/APB bus. This thesis work presents a scheme for development of ASIC based on SPARC processor. SPARC implementations provide exceptionally high execution rates and short time-to-market development schedules.The open source SPARC RTL is to be implemented on 180nm CMOS process. The synthesised RTL is integrated with the above listed peripherals to create custom ASIC for space application. The platform used for it is Xilinx and it is mapped on to Virtex 4/5 kit using GRMON debug monitor. The SPARC processor is simulated and synthesised using Synopsys tool flow and netlist is generated in Design Compiler.Using this approach we can provide the scalability of the cost/performance ratio of successive implementations over the conventional processor.