Implementation Methodology Of On-chip High Speed Interconnect

Abstract

Today in VLSI design, most systems are built using bus architecture for communication.Bus topology will be soon replaced by network on chip which is becoming a backbone for all systems. Mesh is one of the most widely used topologies in this area.Due to a reduction in the size of transistors and ability to pack more number of transistors in the same die, nanometer technology has been introduced in VLSI industry which made the manufacturing process more complex. High speed interconnect technique for the network on the chip is essential for SoC design due to its drastically increasing performance complexity. Lots of challenges are faced by these interconnects to meet area constraints, timing budget and power. Hence the routing pattern we pick for routing the interconnect can have a big impact on the SoC floorplan.High speed interconnect consist of many signals so the routing methods/patterns picked up has a great impact on SoC floor plan. Quality of the interconnect highly depends on the process of execution of synthesis, placement, floor plan and routing. However, advanced design rules, more IP and hierarchical design styles for super-large billion-gate designs, serious buffering problems from interconnect scaling and metal layer stacks make routing a much more challenging problem. This project focuses on IP interconnection method in which the constraints between processing nodes have been analyzed to decide the area, time and power required while connecting one node to another. These constraints also help in deciding metal layers required for routing. This physical interconnect topology also includes the study of deep sub-micron effects like cross-coupling, PVT effects. This project helps in obtaining the optimal solution for a physical interconnect method in terms of area and time and power. This thesis discusses a series of techniques that may relieve this problem and guide the physical design closure system to produce not only easier to route designs, but also better timing quality and power reduction.