Radiation Hardening For CMOS SRAM

Abstract

SRAM Has Become A Major Component In Many VLSI Chips Due To Their Large Storage Density And Small Access Time. SRAM Has Become The Topic Of Substantial Research Due To The Rapid Development For Low Power, Low Voltage Memory Design During Recent Years Due To Increase Demand. The Aim With This Thesis Has Been To Make A Survey Of Radiation Hardened Electronics, Explaining Why And How Radiation Affect Electronics And What Can Be Done To Harden It. The Effects Radiation Have On Electronics In General And In Specific Commonly Used Devices Are Explained Qualitatively. The Effects Are Divided Into Displacement Damage (DD), Total Ionizing Dose (TID) And Single Event Effects (Sees). The Devices Explained Are Mosfets. The Reliability Of SRAM Used In Space Radiation Environment Is Seriously Decreased By Single Event Upset (SEU) And Single Event Transient (SET), Which Poses A Great Threat To The Normal Operation Of Aerospace Equipment. In This Paper, We Propose A Novel Structure Delay Self Restoring Logic (DSRL) Based On SRL. Its Storage Structure Makes Up Of Three Muller C-Elements And Two Phase Inverters. It Separates Read And Write Lines On The Basis Of Structure And Adds Delay Unit And Delayed Bit Line To Write Data. This New Memory Cell Has Got The Ability To Immunize SET In All Working Period Besides Anti-SEU. The Simulation Results Show That Our Proposed SRAM Cell Has A Considerable Lower Failure Probability Among The Considered Recent Radiation Hardened SRAM Cells.