Scan Construction for Design and ATPG Efficiency

Abstract

In todays complex SoC designs the fault spectrum is not only limited to stuck-at- faults, now the spectrum covers faults such as high impedance shorts, cross talk between signals etc. These faults arise at the functional speed of the chip and cause timing related issues. ATE tests a chip at relatively a low frequency (50 MHz) hence these faults arising at functional speed are not detected. This leads to low fault coverage and increased DPPM (Defective Parts per Million) rates. At-speed testing is used to detect these timing related faults. The work described in this thesis helps improving the at-speed coverage without affecting the design performance. Out of LOC and LOS at-speed techniques, LOS gives better fault coverage with less number of test patterns. One of the ways to perform LOS is to pipeline the scan enable signal using a pipeline register. Challenged is to close the timing path from pipeline register to functional endpoint. Timing optimization tool will spend too much of time in optimizing these critical paths and because of this it cannot optimize other important functional paths. Thus overall timing of the design is not optimized. The solution proposed in this thesis is to divide design under test into physical grids and for each grid clone the pipeline register to closer proximity of endpoints. This physical aware duplication creates local buffering of scan enable signal for each partition and the path from pipeline register to scan flip flop is minimized. As the path is minimized now tool can spend enough time for optimizing functional paths. This thesis also explores other ways to achieve better at-speed coverage. Core wrap- ping feature allows different partitions to be tested independently. While doing core wrapping tool adds only a mux before a register. When doing internal core testing the values at cores input ports are unknown (X values). While doing at-speed testing to avoid these X values to pass to the internal logic, scan enable is kept high. This creates additional design burden to converge these paths at functional clock. The enhancement proposed in this thesis adds hold mux to retain the state and helps in mitigating such at-speed paths.