Physical Design Optimization of an IP Core

Abstract

Aggressive scaling down of technology in last five decades, the integrated circuit design has en- tered in the nanometer scale era. As the scaling down may help in production of more powerful

chips, at the very same time designers face a lot of challenges. The physical design stage encounter the most of the challenges. Firstly, with the reduction in the die-size the placement and routability becomes an issue for the design. It may lead to DRC errors or may lead to an unroutable design. Secondly, with the evolution in the fabrication technology the total utilization of the die-size has increased. So insertion of more standard cells in the same die area is possible, with this an issue of congestion has come out. If we insert more cells in less area, than there will be less space for the wires to run, and it will cause the congestion. Thirdly, the processors of today are being clocked over 3 GHz, so timing becomes an issue, so timing of the chip has to be met according to the timing-budget. Fourthly, the power management of the chip, today most of the chip are multi-voltage design, so they have multiple power domains. So the design should be such that it must have power rails of that power domain and also the global power rails, with the power gates or power switches. Also the impact of process variations is also increasing with the shrinking size of the chip. Several important process variations effects show strong dependency on the underlying patterns of the die, these problems can be addressed through appropriate physical design techniques. The common technique is the addition of the derates in the design, which will give some percentage of relax- ation in terms of power, timing and wire delays. In this report, the ideas for solving the routability, congestion, timing, multi-voltage design and several sign-off checks will be given. The sign-off checks will be for Logical Equivalence Checks (FEV), low power checks, timing estimation (STA) checks. The Logical Equivalence Check (FEV) checks that all the cells have been inserted by the tool or not, sometimes the tool may even opti- mize the logic, those checks are also incorporated in the Logical Equivalence Check (FEV). The concepts of Unified Power Format will be very helpful for low power checks. The usage of isola- tions, level shifters, retention cells, power domains is the basic of low power checks. This check determines that the isolations or level-shifters are inserted at proper places or not. For the timing estimation (STA) check the concept of timing i.e. setup and hold timing are very important. If there is a setup violation then according to the type of cells we bound them together and bring all the cells closer so there is no setup violations. Also the setup time of a SoC determines the operational frequency of the chip.