Physical Design & Verification of I/O cells and pad rings for sub-nm CMOS Technology

Abstract

The nano meter era has revealed significant concerns in physical effects, which are now the leading factor in the failure to achieve acceptable yield. A combination of factors that emerge in nano meter scale ICs, such as shrinking feature sizes, finer line widths, longer interconnect and more routing layers have a profound effect on the ability to gain acceptable levels of yield. The basic fundamentals of Input/Output chip design which comprises of Input buffer and Output buffer are discussed. The

several other internal circuits involved such as Slew Rate Control, hysteresis, Level- up shifters, Level-down shifters etc. have been discussed in detail with the respective

pads. These complex system components are being further integrated on silicon to form larger System-on-a-Chip (SoC). However, this same process technology is defined by smaller and more delicate structures that must interface and communicate with the harsh external world with voltages and currents that will easily damage and destroy the IC. The only thing that stands between the harsh external environment and the protected internal environment is a specialized library of I/O pads that handle the buffering, translating and interfacing of external signals from the bonding pad to the internal signals of the core of the IC. The different technology nodes like 28nm FDSOI, 45nm CMOS, BCD9S, H8S is used for designing the I/O layout and pad ring in Cadence Virtuoso Layout Design tool. Layout Design of I/O blocks & pad rings gives the detail information in designing a layout with the constraints to be taken into care and the guidelines for making layout has also been discussed. The Physical Verification tool is used by every major foundries to develop the design rules in order to ensure acceptable design performance in new process technologies. The advancement in semiconductor technologies cause the decrement in the area of chip, because of the following reason Layout Designing in different CMOS technologies has became a challenging task to do. In this dissertation, creation, verification, validation of I/O layouts & pad rings in different CMOS technologies is presented.