Timevision Exploration and SoC Implementation Flow

Abstract

Timing in any design is crucial part, which includes setup and hold time analysis. SoCs are controlling the hand-held buyer gadgets unrest going on surrounding us. Right definition and the board;of timing constraints for a SoC are basic errands. In addition to generating constraints from scratch, the designer can also explore and identify several issues with the design that are relevant for implementation and timing closure. So, Timevision Tool was used to perform the generation and verification of constraints.The Timevision Tool is required the only input RTL or gate level netlist to generate the constraints for implementation and the designer is assumed to have no or very little knowledge about the design and constraints. The issue of design respin where the constraints are reused but functionality has changed, IP coming from multiple sources, and the entire constraints verification process becomes a very tedious task. So, using the Timevision, designers can easily verify constraints in tcl or SDC format.

The dissertation work mainly includes the implementation optimization of an already im- plemented design in terms of PPA (Performance, Power and Area) to make the design more

effective. To achieve either performance or power/area optimization, flow of many different implementation trials were studied and implemented. The different designs achieved were differentiated based on the optimization achieved. Also, some combinational and sequential standard cells were appropriately added during the synthesis of the design according to the re- quirement. After the design has been implemented, the functionality was verified in case the newly added cells affected the working of the rest of the design. All the implementation trials were done in Cadence tools like Genus, Innovus and Tempus.