Performance and Power Optimization in High Speed Design

Abstract

From the last two decades performance of the microprocessors has been advanced at ex- ponential rates. There is a constant shrinking in the device geometry and increase in functionality of the processor. This increase in the functionality and performance has led to the exponential increase of the microprocessor core integration levels and system clock frequency. This trend is known as the Moores law. Earlier VLSI circuit designers mainly focused on improving the performance of a cir- cuit in terms of circuit speed, cost and area. High speed design is one of the desired factors for complex computations. But as the integration density of processor core improved as- toundingly power dissipation also become an important consideration as performance and area for VLSI Chip design. So the challenges in present projects is to get power reduction without much degradation in the performance. This project focuses on design methodologies for high speed CPU blocks. It explains the total flow of the back end design starting from implementing the schematic circuit from given RTL code using standard library cells to final layout. The design will be ful- filled by all the given constraints like operating frequency, timing violations, area, power, noise, reliability, circuit quality, layout quality rules and scan chain insertion for design for testability. Also it includes the different methods of delay optimization, timing anal- ysis and power optimization techniques that can be used in digital chip design.