6T-SRAM Cell Leakage Current Analysis & Self-Timing Circuit In Memory

Abstract

The semiconductor industry has been very creative finding ways to minimize the shortcomings of planar FETs over recent process generations, while seeking a strong

alternative. Finally, a viable alternative has emerged as the FinFET. This evolu- tion of the MOSFET has proven to be the best choice for next upcoming generation

processes but brings with it some new challenges for design and manufacturing that require careful consideration.

Memory presently occupies a large part of system on chip, approximately 60%, there- fore the reduction of power and delay in memory become very important issues. In

such condition it is require to find the cause of power consumption and delay in pe- riphery and array part, if somehow one can remove the sources of power dissipation

and delay, it will improve the performance of the system. So, here I presents the Bitcell analysis and its leakage current analysis, because in the memory array we have lots(billions) of Bitcells and hence its leakage analysis is very important for reducing the leakage. Nowadays we are concern with the low power devices, so we have to apply diffrent techniques for the SRAM for reducing leakage so power consumption reduced, here I

have mentioned the primary work on the memory self-timing circuitry and its impor- tance in this report, it shows that how we can efficiently track the memory instances.

Here we are discussing in detail about read and write margin and how they are help- ing us to reduce the leakage and operational time of memeory. This will lead us to

the faster read operation and low power SRAM operations. It is going to be very helpful for the SRAM Memory design, as here we decrease the power and increase the speed for the same technology and try to track the Bitcell speed.