Validation of Performance Monitoring Architecture in Fullchip Environment

Abstract

With increasing number of cores in multi core processor system, focusing on its functional verification is not enough because the motivation for building such systems is to achieve high levels of system throughput. A functionally correct SoC with poor performance will fail in market. So performance monitoring of such system is an important task before its

tape out. Furthermore, focusing on individual system components for performance mon- itoring is not sufficient. In fact, UNCORE performance is bottleneck for entire system

performance. So focusing on system performance is significant.

With advance in VLSI Technology these days, high density processors enter into mar- ket which provides luxury of hardware Performance Monitoring Unit inside the chip that

monitors system performance accurately. So validating this Performance monitoring unit is overriding task to get reliable information of device performance.

This thesis outlines the architecture of Performance monitoring unit (PMU) in SoC and functional validation of PMU. It covers interrupt based verification and includes flow to validate core and uncore PMU, core and uncore events responsible for performance, validating Performance monitoring counter and registers, coverage implementation and improving coverage at fullchip level.