Pre-Silicon Verification and Debug Improvements in Server Class IPs

Abstract

This project is aiming at pre-silicon verification and debug improvements for the server class IPs. The first part is about pre-silicon verification and the second part is about the debug improvements for sever class IPs. The pre-silicon verification involves three components 1.) Understanding the functionality of the DUT that is to be verified 2.) Writing tests sequences to verify the functionality. 3.) Debug the failure we face during the process. Pre-silicon simulation debugs have grown exceedingly difficult and time-consuming over the past few years with the growing complexity of IPs. This project aims in improving the debug cycle of RTL simulations by building trackers around the RTL pipeline stages, arbiters etc. The trackers will monitor the transaction flow across the complete design and provide enough debug information about the parameters that enable/block the forward progress of transactions. The project also aims to come up with smarter methods to triage simulation failures which help improve debug throughput and efficiency. Debug improvements has been done by writing script and SV Assertions.