Debug Feature Implementation on Intel’s Next Generation Client SoC

Abstract

This thesis describes generic SoC (System-on-Chip) debug infrastructure for reducing back-end

time-to-market while maximizing product quality. Because of increasing complexity of integra- tion, power management goals, and time-to-market pressures, post-silicon back-end validation

and debug have become more challenging. Debug features must be planned and implemented early in a design project to meet market expectations. Most modern SoCs incorporate several IP (Intellectual Property) modules, e.g., CPU cores, GPUs, USB controllers, memory controllers, modems, etc. Some IP blocks are internally developed, while others are developed by third parties. Modern designs often lack compatible debug features between IPs when they integrate various IPs, thus supporting SoC-wide debug and validation is difficult without a defined IP debug integration standard. IP designers must integrate debug and trace interfaces which can easily be incorporated into a SoC. There are many challenges to creating a debug infrastructure

across IPs since each IP has unique requirements and limitations. Therefore, debug infras- tructures must accommodate various nuances in IP requirements. Common challenges include

aligning debug traces across IPs, trace storage, and trace extraction from the SoC for post-failure analysis. There are many trade-offs associated with optimally designing a trace infrastructure. This thesis covers the details of debug architecture,debug triggering, aspects of debug and trace of IP blocks for debugging across an entire system Observing and controlling many different signals from different areas of the SoC, is likely to make the SoC unroutable. In contrast, our approach relies on a new form of reconfigurable

logic, namely a distributed reconfigurable fabric, whose components are inexpensive DFD in- struments that can be widely distributed and can observe thousands of signals, for that we are

integrating debug IPs and various network on SoC. The main difficulty in post-silicon validation lies in the limited visibility for circuit internal nodes, because the circuit under debug is a piece of silicon that has already been fabricated. Integrated Debug ips on SoC as per the debug requirement, Inserted various debug networks throughout all partition in SoC, Engineering change order has been implemented to fix RTL bugs like connect, disconnect nets, add or remove logic, power domain changes etc. after the RTL has been freeze for backend processes.