Analysis and Development of Standard Cell Layout in FDSOI Technology

Abstract

A standard cell library is a collection of low-level electronic logic function such as AND, OR,

INVERTER, flip-flops, latches, and buffers. These cells are realized as fixed-height, variable- width full-custom cells. The key aspect with these libraries is that they are of a fixed height,

which enables them to be placed in rows, easing the process of automated digital layout. The cells are typically optimized full-custom layouts, which minimize delays and area. So Standard cells play a vital role in the soc.

Process variation in transistors performance has become a key problem in deep sub-micron

CMOS technology circuits. In 65nm process node and beyond, this variability plays an impor- tant role in chip performance.This variation is due to deviations in the semiconductor fabrication

process.In order to improvise yield of the product, worst case design approach needs to follow

which will results in optimal IC performance.This can be achieved by pre silicon and post sil- icon validation.Pre silicon validation is done by Monte Carlo and cross corner simulation.Post

silicon validation is done by specially designed sensors.

The first step in the designing of any standard cell is to design the schematic using minimum number of transistors involved. Depending on its end use the schematic can vary for the same logic operation. If area constraints have to be prioritized over the cost then a different design will be used for the same logic and vice-versa for cost constraints.

The resulting layout from the schematic is passed through various checks to confirm its func- tionality on silicon. DRC (Design Rule Check), DFM (Design for Manufacturability) and LVS

(Layout v/s Schematic) are different checks to do so. Based on the results of these checks the standard cell is said to be functional or non-functional.

After physical verification, parasitic extraction is carried out to get parasitic device parameters like resistances, capacitances. Parasitic extraction is carried out to get the knowledge about extra power consumption, delay, noise, IR drop etc. Results of parasitic extraction is used for further analysis like static timing analysis, noise analysis, IR drop analysis, logic simulation etc.

Next step is process variation analysis which is also called worst case analysis. There is a need to check whether the device will perform under worst environmental condition or not. Monte Carlo and Cross Corner simulations are carried out. If device is failing then there is need to change layout of the device.

Process Monitoring Box is used for on chip process monitoring.Detailed analysis of sensor de- sign is carried out. Sensors are used for different purpose like to detect process of nMOS/pMOS,

process variation compensation, leakage monitoring.