Frontend Validation of Memory Subsystem in SoC

Abstract

In memory domain LPDDR4 is the latest technology which is designed for optimizing and increasing high performance, low power and to boost speed for mobile devices like smart phones, tablets & ultra thin notebooks. It operates at the rate of 4266 MT/s,

which is nearly twice to LPDDR3. Here for low power LOW VOLTAGE SWING TER- MINATED LOGIC technique is used which is effective upto 50 percentage power save

compare to LPDDR3. As speed and size has been improved using latest technology, ver- ification of LPDDR4 DRAM and entire memory subsystem becomes more critical and

challenging. Here i have tried to verify some basic features of LPDDR4 as well as of

Memory Subsystem. I have a written code for scoreboard and sequences for data gener- ation to verify different features of memory subsystem.