Layout Convergence in Lower Technology Nodes

Abstract

With the advancement of technology, millions of transistors are implemented on a single die area resulting smaller and smaller size of a particular chip. This has increased the complexity of the manufacturing process. Before sending a layout design for the production, it is verified against some design rules to check whether this physical structure will be supported by manufacturing equipment or not. Layout verification is the area which covers the verification of the layout design by measuring dimensions and density in each small window of the design. It is mainly concerned with the checks performed after each stage in physical design to reduce design cycle time and to verify the manufacturability of the layout with higher yield. These checks are automated mechanisms provided to verify the layout and power supply connectivity for robust and converged design at lower technology. With the enhancement of technology, the different types of issues come into the appearance which requires modification of these mechanisms accordingly so that it can reflect all such violations which are not going to be satisfied as per the technology requirement. All these violations and issues are needed to be considered and individual focus should be provided to know the reason of each violation and how it can be resolved. Based on the count of the violations and type of the problems either manual work or automation script is provided to make layout to be manufactured perfectly with the foundry specific design rules. This project includes the various types of checks which are provided to verify the manufacturability of a chip and different cases of violations and how these are going to be resolved. The project also includes various automation scripts written to resolve the violations.