Characterization of Standard Cell Library and Benchmarking

Abstract

In semiconductor design, standard cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. The Standard Cell Library contains a collection of logic gates over a range of fan-in and fan-out. Besides the basic logic function, such as inverter, NAND, NOR, XOR and Flip- Flops, a typical library also contains more complex functions such as Multiplexers, Full-Adder, Comparator etc. Characterization is a process of analysing a circuit using static and dynamic methods to generate models suitable for chip implementation flows. Creates electrical views (timing, power and signal integrity) in industry standard formats such as Synopsys Liberty (.lib) format. In digital IC design, the standard cell-based design is the most used in the industry. It accounts on a mature validated cell library to quickly design a reliable commercial IC. However, cell libraries are constantly modified, and a series of validation tasks are employed to guarantee correct IC design and fabrication. Assessing the comparative performances of several Standard Cell Libraries in a reliable way is a tricky project as it deals with statistical issues. The methodology traditionally used in the industry to benchmark Standard Cell Libraries is the so-called “cell-by-cell” approach. Benchmarking consists of taking one or two basic cells, such as a NAND2 and/or a FLIP-FLOP, and comparing their area, dynamic power consumption, leakage and speed. Benchmarking is an important component of library selection. Almost no interesting standard cell tradeoff can be measured without benchmarking. Target frequency, logical IP, metal stack, EDA tool chain, power and clock distribution style, etc. all interact with different standard cell implementation choices in different ways. This requires a methodology which enables many different variables to be tested in combination in parallel. Standard-cells are crucial elements of all SoC/ASIC designs, constituting a dominant portion of the design, both in terms of the device count of the chip, as well as in die area. Standard-cell performance in the timing critical paths of designs, and their energy efficiency in terms of leakage and dynamic power, have a direct bearing on the PPA (performance, power, and area) and cost of the chip.