Automation of Design For Test Flow-Focus on Faster Execution Cycle

Abstract

This thesis focuses on the Design For Testability (DFT) part of the Pre-Silicon designing stage of an RF chip for client platforms. DFT is the process of inserting some standard test modules for checking an RF chip's testability. The process of creating such mod- ules involves designing of various modules like Scan, BIST etc. The thesis further goes into the process of generating memory views, creation of memory-wrappers using vari- ous third-party tools being performed on the Linux environment. The process of DFT includes numerous steps like Architecture design, RTL coding according to the given re- quirements, and Verification followed by Synthesis, Gate-level simulation and DFT logic insertion. It also includes integrating various Intellectual Properties (IP) from diffierent Business Units (BU) or workgroups to be put onto the System on Chip (SOC), into which embedded memories are a part of them. The thesis explains the scope of embedded mem- ories, memory wrappers and their generation process using a shell script operated Library generator and parallel ow commands respectively. It also gives a brief knowledge on in- troducing some of the automation into the p ow steps, which requires the least possible user input and can reduce the number of steps for the process.