IR Drop Analysis Across Voltage Domains to Check the Timing Impact on Arm CPU Implementations.

Abstract

Few years ago, the main concern was performance and chip size in the IC industries. A tool was developed to maximize performance and minimize area of the chip. In between the trade-off of performance and area, IR drop become most challenging issue in the industry. Complexity of chip gets increasing day by day as the technology shrinking. Designing a robust power grid has become a major challenge with shrinking technology allocating more performance in a smaller area. The drop in voltage of power grid can significantly affects the standard cell and net delays. It degrades transitions dynamically in the design. It will also affect timings of the design. Currently, flat derate approach is used in the industry. Which makes design more pessimist or optimistic. Flat derates are applied directly on the cells, that may or may not require by cell. So to go beyond this into the real world scenario of chip where actual voltage consumed by the cell and drop occur across metal strip. A new approach has been familiarizing for accurate results which leads towards reality of actual behaviour of chip after manufacturing. This approach is mainly based on the IR Drop at particular instance and Analysis its delay and how much it affects the timing at that voltage.