Optimizing Processor Power Management Veri Cation by Reducing Redundant Simulation Cycles

Abstract

The Pre-silicon verification is done to validate processor IP using simulation. Verifi- cation can be done using simulation and emulation. Simulation involves modelling of the processor and verifying its functionality in a given time period. Emulation uses replica of the exact hardware model and is much faster than simulation. This project is within the limits of software simulation to validate the power management ows of the processor. The simulation of power ows contribute to the major portion of the test run time and contain many redundant cycles. The simulation time can be optimized by reducing the redundant cycles. This requires analysis of the ow for identification of redundancy. This reduction is carried out at two levels- electrical ow; which involves the state machines and logical ow; which is done at the micro-architectural level of the processor. This involves techniques like Test Bench injection and Backdoor Access of registers. Forcing some signals into the test bench based on some conditions helps to move the processor to the next state in less time. Backdoor access ensures the load and store of registers in zero simulation time. This experiment is carried out for C6 ow of the processor. There is approximately 28 % save in the electrical ow and almost 14 % save in the logical ow. This single test saves a significant amount of time. For regression, there are thousands of test running. Saving some amount of cycles for each test would result in a significant reduction in simulation cycles. This reduction in simulation cycles will help in encapsulation of more number of test cases in the same amount of time, thus improving efficiency.