Clock Route Optimization

Abstract

For the high speed core design clock distribution is one of the most important factor to achieve the best possible result in terms of clock arrival time. Distribution of the clock across an entire chip is a challenge to maintain the balance between power and clock skew. The performance of any digital system significantly degraded due to existence of huge delay through clock routing topology. Clock arrival time is mainly dependent on the clock routing length and capacitance and also excessive delay is obtained due to presence of long signal routes in core. To minimize the routing length and RC value of a clock as well as clock arrival time. An algorithm is proposed to find the optimize placement of global driver. Optimize placement of global driver is obtained by finding the location of all the receiver pins of clock net island taking the average of all the receiver fub clock pins which is connected to the global driver pins through the clock net helps to find the centroid of that particular clock net island.