Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/9254
Title: Semi Custom Design of Functional Unit Blocks for High Speed Micro Processor
Authors: Shah, Heta
Keywords: EC 2017
Project Report
Project Report 2017
EC Project Report
EC (Communication)
Communication
Communication 2017
17MECC
17MECC18
Issue Date: 1-Jun-2019
Publisher: Institute of Technology
Series/Report no.: 17MECC18;
Abstract: Every year microprocessor core is shrinking in size owing to the advancement in technology and decrease in technology node. These evolutions have given excellent platform for fabricating very high-performance and multi-core processors with sev- eral new features. However, these changes also present newer challenges which are even harder to meet. For example, fabrication of devices of such smaller size in itself is difficult. From design perspective though we face various issues which hamper or progress while designing. The new challenges include more stringent and rigor- ous performance targets compared to previous project. Performance targets include area, timing as well as power parameters. In this project our aim is to improve on all these parameters so as to achieve higher quality of design. With every new design of microprocessor core there can be a requirement of new features to be added to the existing once. This feature update is incorporated in our design through RTL change. We will be working on one such update in this project and accordingly check its effect using various factors. How we accommodate such changes while still improving our design is shown in this project. We use enhancements over existing design technologies in order to use goodness of the previous core design. This not only saves designers time but also makes it comparatively easier to deliver high quality end product. This project work shades light on design ows, design optimization techniques (both timing and power) as well as quality checks for sign off. We perform Reliability Verification check in order to enhance over value of the design. The techniques mentioned in this project work are tested and results analyzed to gain confidence on the methods. These meth- ods can be used to achieve timing optimization, power optimization and improve the overall quality of our design. Frequency push and power reduction both have become important now due to shrink in technology. Timing performance though still dominant, power has started to become a bottleneck for our processors as the competition is now closing on the gap.
URI: http://10.1.7.192:80/jspui/handle/123456789/9254
Appears in Collections:Dissertation, EC (Communication)

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