Subsystem Testbench Development and Verification using System Verilog UVM

Abstract

A large System on Chip (SoC) has millions of interconnects between modules, sub-modules and ports. Verifying that these connections have been made cor- rectly is an important step in the verification process.This is commonly begins with simulation, and then proceed to formal verification. Both methods begins with a specification of all the required interconnects and are then meant to verify that all the inputs, outputs and paths between modules (i.e. Source and Des- tination nets) are connected as expected. The physical number of connections to check is one issue, as designs contain thousands of wires which potentially all need to be checked for correctness. Debugging presents a secondary though often equally challenging issue. The reason is that although checking the con- nectivity with dynamic tests using a directed or constrained random approach will certainly find some of the connectivity bugs, any problem will show up only as a functional issue inside the blocks under test, which doesn’t neces- sarily help in pinpointing the problem connection. The work has been carried out in this project is showing how connectivity checks can be done for such complex designs like modules connected by AXI protocol, modules connected to sub-modules and how identification of connectivity failures between modules and sub-modules. Disk Space is also a issue. if user starts running regression in disk which has not enough space then regression starts hanging or suspended. so a shall script has been developed to manage disk space by notifying user to cleanup their unwanted data from hard disk. In this script first it creates data base of every disks, the database contains user’s folder location and user’s name. then a unique list is created and from that unique user list script searches for folders user has created from the database. using list of user’s folder lists it counts their usage and a notification mail is sent to the users.