Timing Analysis and Test Structures

Abstract

Timing analysis and Setup Hold analysis plays a major role in designing any Test-Chip. In modern CMOS circuits, meta-stability is one of the major growing concerns especially when the frequency is increased and the time is reduced. Meta-stability is a state where output of a system is unstable for unbounded period of time. This occurs when there are setup and hold violations in the circuit. In this state, the output may unable to settle at logic ‘1’ or logic ‘0’ in the required time for proper operation of the circuit. As a result, the circuit may behave in an unpredicted manner causing a system failure. The effect of the failure arising from the metastable behavior is troublesome and mysterious because they are irregular and virtually untraceable. Reliability of the system is negotiated when the sequential element like flip-flops, arbiter or synchronizer goes in meta-stable state. In flip-flop, meta-stability occurs when the data input and the clock signal transitions at the same time. The amount of time output remains in the meta-stable state depends on the technology of the design. The relative stability of the states logic ‘1’ or logic ‘0’ is much more stable at the base than the somewhat stable state at the top of the hill (quasi-state). However, there is a finite probability of a circuit being not able to resolve its meta-stable state correctly in given time. To fix this, models have been designed that describes the failure mechanism of the latches and flip-flops.

Therefore, it is very important to understand the behaviour of meta-stability in input output. Good synchronous design practice can achieve high reliability. In this thesis, a test structure design to characterize the Setup/Hold violations of the DUT at the meta-stable condition is mentioned. The test structure was implemented at 28 nm technology using Cadence tool.