Validation of SoC Design using Hardware Emulator

Abstract

In today's era Everything we know keeps shrinking while intelligence is added to Microchips everyday. New Algorithms/methods for Machine Intelligence keeps raging towards empowerment. Thus, looking from an hardware perspective, the complexity in terms of power, area & thus performance are either improvised or compromised elsewhere inside a Chip. it becomes necessary & essential to introduce a validation stage to the silicon development cycle at such complexity levels. For critical applications such as space, military, High Performance, industrial where Hardware failures inside a chip are not acceptable once on fields. Especially in applications where human reach isn't a feasible way to debug & fix the issue, a validation stage is what promises the application to be running hazzle/bug free at least for critical bugs. A pre-silicon validation which happens before fabrication of actual silicon is what ensures that the SoC will work as expected as the real Silicon. This thesis explains about various techniques used in order to achieve pre defined validation goals. New topology/method has been explained/implemented here which gives reduction of human intervention workload, complexity & time.