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http://10.1.7.192:80/jspui/handle/123456789/9380
Title: | Power – Grid Creation, Analysis and Evaluation on Industry Technology Nodes |
Authors: | Bhatiya, Hepi |
Keywords: | EC 2018 Project Report 2018 EC Project Report EC (VLSI) VLSI VLSI 2018 18MEC 18MECV 18MECV01 |
Issue Date: | 1-Jun-2020 |
Publisher: | Institute of Technology |
Series/Report no.: | 18MECV01; |
Abstract: | Power Grid design is becoming increasingly challenging in lower technology nodes due to the high power density demand. Because of this Power delivery network (PDN) engineers face difficulties in addressing some of the unique requirements for their designs. Traditional way is to make a global power mesh with uniform density for the entire design without considering the power demand of various blocks, which are present in the design. This mode of work which is largely design-independent for a given technology often results in a huge over-design. Thus the aim of this work is to develop tcl utilities in existing design framework to simplify the power grid generation task for complex designs. The die PDN is split into two main sections, 1. Redistribution layer (RDL) or the top level design and 2. Partition level grid design. Mainly we are going to focus on partition level grid design. Partition grid design comprises of lower level metal layers which are used for both signal and power routing. The goal is to make tcl utilities for a design that satisfies IR/EM goals for different power \& utilization design constraints. Another critical aspect of grid creation is via creation from lowest level metal to top metal while aligning the vias to tracks and being Design Rule Check (DRC) compliant. The grid creation task become complex as design rules for vias and variable metal spacing create many candidate alternatives from which we need to choose the most optimal solution. Thus, this work also assesses which type of via laddering, given a set of metal shapes and via specification. Another key aspect is that once designed, the PDN grid would not change throughout the design flow starting i.e from floorplan all the way through post signal routing. Hence after power grid geometry is generated by our tcl utility, we perform static and dynamic analysis to evaluate the most optimal suit for PDN of the design. |
URI: | http://10.1.7.192:80/jspui/handle/123456789/9380 |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
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18MECV01.pdf | 18MECV01 | 5.95 MB | Adobe PDF | ![]() View/Open |
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