Interconnect Optimization For Dynamic Power Reduction

Abstract

Modern ASIC designs having ultra-deep sub-micron processes and for this type of technology node layout had very important role to play. Full chip layout had its own hierarchical structure. The full chip hierarchy contains Standard cell, Functional unit blocks (fub) and Section(partition). Fub Integration Flow is useful to integrate the fub inside section. It basically loads all the fub data inside section, then perform hook power on it and check for the opens, DRC violations, design for manufacturability, etc. Sections have many fub to integrate in cyclic manner and have many DRCs violation over the fubs. To clean all the DRC violations manually is time consuming process.

Routing has become increasingly challenging with each technology node due to the ever-increasing number of metal layers and distinct layer thicknesses, design rule volume, and design complexity. In this context, the problem of congestion analysis or prediction also increases in significance, since designers need to be able to predict during early floor planning and timing closure iterations whether their design will route. Further, it is not enough just to route cleanly; the designer requires that the routing be completed with minimal disruption, to avoid massive post-routing timing and power degradation and electrical fix ups.

This thesis covers the methods to reduce the dynamic power of the power-hungry nets by reducing the dynamic capacitance (Cdyn). After that, an automation flow is developed for these power reduction techniques by using TCL scripting so that the overall human efforts can be reduced.

By these methods, I got an improvement for around 5% nets of the project thereby giving me a considerable power optimization overall. And, a good amount of human efforts and time are saved by using the automation flow on each partition.