Full Chip Timing Analysis: Scope for efciency Improvement

Abstract

Leading high performance design extensively require clock-tree mesh (CT-MESH) for balanced clock distribution across SoCs. But STA tool PrimeTime can’t model multi-driven clock mesh network in timing models. The mesh delays are then back annotated into STA run along with guard-bands to account for variation and aging. This adds overhead in terms of execution, increases turnaround time and adds signoff risks since, the designer needs to ensure correctness and accuracy of spine delays. CT-Mesh are a well-known clock distribution architecture meeting design requirements of distributing critical global clock signals on a chip. Clock network can have variations due to non-uniform switching activity in the design, intra-die process variations, asymmetric placement of circuit elements and manufacturing defects on atomic level. The mesh present in CT-Mesh averages out these undesirable variations between any two signal nodes contiguously distributed over the die. But its utilization is affected due to difficulty in analyzing them with sufficient accuracy. This thesis describes an approach using PrimeTime to analyze clock mesh network accurately using SPICE simulation.