SystemVerilog Assertions based Arbiter Verification

Abstract

Every year digital designs are observed with increase in complexity. With complexity growth, dramatic shifts in design and verification methodology have occurred. One such shift is SystemVerilog (SV) which is hardware design and verification language. SystemVerilog Assertions (SVA) increases the quality and efficiency of verification as it shouts failure right at line of design code. Thus SVA are efficient option to verify design. Assertions verify the test has covered the feature required in design to verify. Reuse of assertion properties is another advantage in verification methodology. Assertions also provide functional coverage and reduce debugging time.

The project starts with verification environment in SystemVerilog language. First In First Out (FIFO) buffer is taken as DUT for verification but connecting FIFO pins with protocol based interface was quite challenging. Verified FIFO with complete SV testbench with varieties of data packet is transferred through interface. Later SVA were applied to verify FIFO outside the testbench using bind operator as the interface signals were different than DUT signals.

As number of data masters increases in SoC chip, the communication within entire system gets complicated. Here arbitration schemes helps with the performance of the system largely. System throughput is affected by the arbiter design block which controls the grant for various requesting masters. An arbitration schemes are usually chosen based on requirement. The project further follows with assertion based verification on Arbiter Schemes. Round robin arbiter and weighted round robin arbiter are developed using SV language in this project. Verification process starts with SV testbench with randomised request pattern. The next phase is ABV (Arbitration based verification) on both arbitration schemes. There are many ways to apply assertion properties for verification. The assertion properties implementation for modules like weighted round robin arbiter is really challenging.