Low Power Veri cation of Data Manipulation IP using UPF Methodology

Abstract

A decade ago, the major challenges of semiconductor device design were performance and area. Designers used to aim at achieving the required target speed in as minimum chip area as possible. Power was not of major concern those days. With the increase in the demand for high performance and high-speed VLSI systems has shifted the fo- cus from traditional performance parameters towards the analysis of power consumption. The power budget and management among the domains of a system is of real concern. Hence, the power aware design using clock gating, power gating, dynamic voltage scaling and frequency scaling are the most used design techniques. Employing such low power techniques at the RTL creates new design and veri cation challenges. The challenges are: how can one domain be power downed, how can it be put back to power up state and do they retain or restore the previously computed data and still function correctly. These can be answered and implemented using new methods of implementation and veri cation using the uni ed power format (UPF) standards for low power intent designs. UPF is an IEEE 1801 standard format to describe the power architecture, also called as power intent, including power network connectivity and power reduction methods. It en- ables veri cation of power intent at early phases of the design cycle. The UPF developed should be consistent with the design at all stages of the design cycle and it should be updated according to the modi cations made in the design. This thesis covers power management concepts like power domains, isolation, retention, level shifter and its speci cation described using UPF. Normal RTL design is simulated using Synopsys VCS and synthesis is done using Synopsys Design Compiler. Low power veri cation is done using VCS NLP (Native Lower Power) and synthesis is done using Synopsys Design Compiler. I have also created library le (.lib) and compiled using Syn- opsys Library Compiler for synthesis of RTL design with UPF. At last we have compared the results of normal and low power synthesis and simulation. Based on low power ver- i cation, in actual IP all the functional test cases are enable with low power simulation mode and check the functionality.