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http://10.1.7.192:80/jspui/handle/123456789/9388
Title: | Validation of Machine Learning Accelerator IP |
Authors: | Jain, Kushal |
Keywords: | EC 2018 Project Report 2018 EC Project Report EC (VLSI) VLSI VLSI 2018 18MEC 18MECV 18MECV09 |
Issue Date: | 1-Jun-2020 |
Publisher: | Institute of Technology |
Series/Report no.: | 18MECV09; |
Abstract: | Artificial intelligence (AI) is the simulation of human intelligence processes by machines, especially computer systems. These processes include learning (the acquisition of information and rules for using the information), reasoning (using rules to reach approximate or definite conclusions) and self-correction. An AI accelerator is a class of microprocessor or computer system designed as hardware acceleration for artificial intelligence applications, especially artificial neural networks, machine vision and machine learning. Neural network processors (NNP) are a family of neural processors designed by Intel for the acceleration of artificial intelligence workloads. The NNP-I and the NNP-T are intended for two different markets, inference and training. “Training” is the work of creating and teaching a neural network how to process data in the first place. “Inference” refers to the task of actually running the now-trained neural network model. Convolution Neural Network (CNN) is a type of deep neural networks that are commonly used for object detection and classification. State-of-the-art hardware for training and inference of CNN architectures require a considerable amount of computation and memory intensive resources. This complex design requires a very efficient verification environment. Tasks described in this report are helping in improving the quality of verification environment, reduce the verification timing, ease the process of debug and coverage improvement. As a part of this project completed multiple activity like creation of OVM test bench for fine granular testing of converters in IP, Coverage Analysis for finding gaps in the tests, integration of a bridge module at IP verification level to reduce the turnaround time due to bugs in the design. After implementation of all this activity there is 66% reduction in turnaround time, 20% reduction in debugging time and coverage is improved from 42% to 85%. |
URI: | http://10.1.7.192:80/jspui/handle/123456789/9388 |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
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18MECV09.pdf | 18MECV09 | 1.77 MB | Adobe PDF | ![]() View/Open |
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