Implementation of safety and security features in Network-on-Chip

Abstract

VLSI Design has entered into a mature stage. Big and Complex Designs are developed by the integration of IP Cores and multiple instantiations of different components. Networks and IPs are common nowadays on the chip. Network-on-Chip needs to be designed for high throughput, low power, and area efficiency. NoC consists of main network interfaces, processors, routers, and switches, with a buffer for flow control implementation which all works in different clock domains. Basically here IPs communicate with each other in terms of data packets containing a header and useful packet information. Looking to the industrial scenario of IP Cores from different vendors and to protect data from corruption safety and security feature needs to be implemented in the design for protection purpose. This work covers the details about the different kinds of implementation of safety and security features at the interconnect level on the chip.

Here First in First out (FIFO) buffer element are developed for the purpose of storage of data bits. As per the safety features Even/Odd Parity, Longitudinal Redundancy Check (LRC), Checksum and Cyclic Redundancy Check (CRC) algorithm modules are implemented in the design for the purpose of error detection. Hamming and Hsiao ECC is implemented as purpose of single error correction and double error detection. All this designs are verified through waveform using Xcelium tool and notable area & timing analysis is done by writing tcl and Sdc file for synthesis flow using genus tool. Security feature helps to make a secure design with the use of PPROT signals in Advanced Peripheral Bus (APB) protocol by driving slave error (SLVERR) and decode error (DECERR) if unwanted transaction occurs at any of the interface IP.

The designed safety and security feature algorithms are integrated with IP for the protection purpose. Due to this implementation of Checksum logical correction for change in any data bits position is improved as compare to Parity and LRC as they don’t able to detect even bit errors. Using Parallel CRC there is 2% saving in timing as compared to serial CRC as it accepts n-bit data at single clock cycle. Using Hsiao Algorithm, there is 12.2% advantage observed in terms of area and 17.2% saving in terms of timing as compared to Hamming Algorithm.