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http://10.1.7.192:80/jspui/handle/123456789/9395
Title: | Magillem based SOC integration |
Authors: | Prasad, Rishabh |
Keywords: | EC 2018 Project Report 2018 EC Project Report EC (VLSI) VLSI VLSI 2018 18MEC 18MECV 18MECV16 |
Issue Date: | 1-Jun-2020 |
Publisher: | Institute of Technology |
Series/Report no.: | 18MECV16; |
Abstract: | The SOCs (System on Chip) are complex systems that can contain multiple Hardware accelerators IPs (Intellectual Property) and many processors for the execution of software application. SOC integration is a complex process as it requires to connect many different IPs together which are supplied by various vendors to create one system. Hence, a need for standardisation arises for IP integration process independent of the vendor providing the IP. For this purpose, IP-XACT based XML is used. Magillem tool is one such tool which enables the user to generate, integrate and create IP-XACT based XML. Also, RTL netlisting in any of the HDL like VHDL or verilog can performed for the top module after integration process. Magillem tool is used in this project for IP integration. In this project a SOC integration is performed for a RADAR based SOC with its application in automotive domain. The SOC consists of digital as well as AMS IPs. For AMS IPs appropriate digital models were created so that they can be come at par with other digital IPs for integration at a common platform which was magillem based platform in this case. For digital IPs IP-XACT format was used for sharing IP metadata which helped in selection of correct IP configuration for the given application from various IPs which are available from different IP vendors. As the complexity of IPs is very high at SOC level with multiple ports to be connected it difficult to connect all the ports at level properly at RTL level. This problem is further exacerbated when the interfaces keeps changing rapidly. The solution to this problem is using architecture level of abstraction for IP integration. As multiple RTL ports are related in term of their functionality they can be grouped as a bus. Then these bus interfaces at architecture level of abstraction is used for IP integration. The performance gain achieved while using this strategy is explained in the report. For analog IPs the communication takes place with the help of registers. Registers are defined as part of IP-XACT based excel sheet as input. Magillem tool can generate the register RTL and IP-XACT compliant XML based on the input provided in register excel sheet. This provides a great enhancement over manually generated RTL for register which is difficult to update every time the register description changes. This project uses this methodology for generation of RTL and IP-XACT compliant XML in place of manual RTL development to achieve the performance gain and save the IP development time. |
URI: | http://10.1.7.192:80/jspui/handle/123456789/9395 |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
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18MECV16.pdf | 18MECV16 | 2 MB | Adobe PDF | ![]() View/Open |
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