Automatic Test Pattern Generation and Simulation for Multimillion Gates SOC

Abstract

With the continuous innovation and advancement in technology, the feature size of transistor is shrinking thereby challenging the Moore's law. The no. of transistor on the SOC is increasing at very a fast pace. With every chip fabricated, its reliability and testability are of major concern. Reliability means proper/expected functioning of SOC in different operating conditions for a greater life time. This is guaranteed by a good design practice and testability of the same. Keeping in mind the investment in terms of time, effort and finance, it is of utmost importance that we obtain maximum possible yield simultaneously reducing the time to market while fulfilling the speed, performance and area requirements. Design for testability incorporates various method/techniques to make it possible to detect faulty design or/and defect. The Defects in fabricated chips are modeled as fault and detected in the design. DFT is involved in almost in every stage of the ASIC design flow. This thesis gives an overview of the DFT techniques namely scan insertion, LBIST, ATPG, Stuck-at and transition fault modelling. It explains the steps of ATPG and Simulation at the block level for different modes. For Stuck-at, at-speed and LBIST patterns are generated and simulated using TetraMAX and NCSim tool. Target of this thesis is to achieve maximum fault coverage with minimum no. of patterns and also try to reduce test time and pin count. The fault coverage to be achieved for Stuck-at, at-speed and LBIST is greater than 99%, 90% and 90% respectively. This percentage is decided based on the line of the product and the risk involved.