Comparative Analysis of UVM TLM1 with TLM2 Interfaces

Abstract

In the era of rapid increase in the complexity and functionality of SoC, their verification is the main bottleneck. More than 70 percent of the total ASIC Design cycle time is consumed by verification. Hence, there is a need for robust and reusable verification environment. UVM -Universal Verification Methodology defines a set of standards or process that enables efficient verification, which is reusable and interoperable. TLM interfaces used as communication mechanism between verification components and also used to model things in various abstraction levels. The aim of this project is to implement the TLM1 ports/interfaces in the UVM based testbench and compare it with TLM-2.0 interface. This paper consists of basic understanding of SystemVerilog testbench environment and UVM testbench environment.

Learnt and implemented various SystemVerilog constructs which are useful to build the SystemVerilog based testbench environment like the dynamic array, queues, mailbox, interfaces, clocking block. Thus, developed the SV testbench with the full understanding of every block and each component. Developed the glue logic which helps in driving data from interface signals to the DUT and vice versa. Verified FIFO by compiling and simulating the testbench in Cadence tool and waveform obtained with the help of simvision tool. Learnt and implemented different types of TLM-1 interfaces first to connect between two components. These TLM connections are independent unlike mailbox in SV. Developed UVM based testbench using the TLM connections. The FIFO is verified using it.

This project discusses the advantages of UVM based testbench over SV testbench. This project compared between the characteristics of TLM-1 and TLM-2.0 interfaces.