Overall Execution Efficiency Improvement in PLL Deliverables

Abstract

Formal Equivalence Verification (FEV) method is used for checking the logical equivalence between the RTL and gate level netlist. It has become essential part of the design flow and has been leveraged for later hand edit such an Engineering Change Order (ECO). It is an exhaustive verification method that verifies design functionality completely without the use of test vectors. As there are rapid advancements in level of integration in VLSI design over few decades, EDA tools plays a vital role in the design, verification and debugging of larger digital circuits. EDA tools offer lot of opportunities to design variety of electronic chips containing the integrated circuits. To meet the functional and performance goals within a design time schedule and cost associated with it presents the scope for EDA tools. Cadence Conformal Logical Equivalence Checker is the powerful efficient tool used for logical equivalence.

After passing through FEV, synthesized netlist parse to Structural Design (SD) Flow. It deals with the implementation of RTL codes into real physical transistors which can be manufactured at a FAB. There are multiple steps in the flow and each stage is focusing on a specific goal. The flow is tool driven i.e. not through manual layouts. Tools such as IC Compiler and DC compiler from Synopsys are used for SD flow. There are specific programming/scripting languages used to direct the tool. To reduce sub block level DRC errors, Dummification flow is developed. This flow improves the LV analysis and closure time by filtering the sub-block LV errors. This flow makes easier to debug block level Design Rule Check errors.