Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/9522
Title: IP Independent Generic Framework to accelerate Development Process Iteration
Authors: Saraiya, Gahan
Keywords: Computer 2018
Project Report 2018
Computer Project Report
Project Report
18MCE
18MCEC
18MCEC10
Issue Date: 1-Jun-2020
Publisher: Institute of Technology
Series/Report no.: 18MCEC10;
Abstract: Intel System on a Chip (SoC) features a new set of Intel Intellectual Property (IP) for every generation. BIOS involves development of major individual components such as Processor, Graphics/Memory Controller, Input/Output Controller hub, System Monitor/Management Bus, Direct Media Interface, SATA/IDE/USB, Peripheral Component Interconnect (PCI), Voltage Regulator and Advanced Configuration and Power Interface (ACPI) for every Intel System on a Chip (SoC). Section 1.1 describes all the basic information required on the Intel SoC. Section 2.1 involves the design of the Basic Boot Flow of the BIOS followed by Section 2.2 and Section 2.3 explains the architecture and protocols which are the concept used to build the proposed framework which is described under Section 3.1 to aid the development and debugging iteration for various stakeholders including but not limited to BIOS Developers, Validation Engineers, Automation team. The framework is designed and implemented to aid the development process by eliminating longer duration of common debugging steps and providing a sophisticated way to build and test the various scenarios includes but not limited to Setup Options, Firmware Flashing, UEFI Variable Creation.
URI: http://10.1.7.192:80/jspui/handle/123456789/9522
Appears in Collections:Dissertation, CE

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