Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/10513
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dc.contributor.authorHazra, Anisha-
dc.date.accessioned2022-01-21T11:10:01Z-
dc.date.available2022-01-21T11:10:01Z-
dc.date.issued2021-06-01-
dc.identifier.urihttp://10.1.7.192:80/jspui/handle/123456789/10513-
dc.description.abstractArm’s processors are based on A, R and M series of processors where Cortex-A series is for application processors, Cortex-R is for real time purposes and Cortex-M is used in microcontrollers. This Project emphasizes on the Performance Analysis of Arm’s Cortex-R Series processors. This family of processors are used in applications where we need fast and deterministic processing and high performance. Their functionality needs to meet challenging real-time constraints in a range of situations. All these features are combined in a performance, power and area optimized package which are the most important factors in today’s VLSI Design scenarios. The Performance Analysis of such processors has been done with the help of certain Industry standard benchmarks like CoreMark, Dhrystone, EEMBC, Automotive, Consumer, Networking, Office, Telecom, FPMark, Stream etc. These tests are written in C and cannot run on cores and hence compilers like Arm Compilers or GNU Compiler Collection are used to convert those tests from c files into binary executable files. The performance can be further optimized or enhanced with the help of optimization flag options during the binary build. Performance Analysis can be either Emulation or Simulation based. Emulator used in this project is Veloce/Strato which is an Emulation tool by Mentor Graphics. Simulation based analysis is done on Cycle Models. Improvements to the existing performance numbers is done by updating the platform files also. In this project the Cortex-R8 processor has been added to the Unified R-Class System by tuning its Read and Write Latencies to that of the common latency of the external system. Verdi Synopsys Tool is used for the Waveform generation purpose. After fixing the latency bug, performance and code size calculation is done, the data of which is further used for the System Analysis of the Cortex-R Series processors. To automate the process of speed and code size calculation, a python script has been used which calculates the performance numbers and code sizes and prints them in a CSV format file. This file can be uploaded to Tableau Software to create graphical representation of data and dashboards. During this project, the Dashboard refresh has been done each time whenever there is a new compiler version release. The current data is always compared with the previous version which keeps a check on the CPU core performance as well as the Compiler performance. Sometimes huge difference in data can be either due to Performance bug or due to Compiler bug.en_US
dc.publisherInstitute of Technologyen_US
dc.relation.ispartofseries19MECV02;-
dc.subjectEC 2019en_US
dc.subjectProject Report 2019en_US
dc.subjectEC Project Reporten_US
dc.subjectEC (VLSI)en_US
dc.subjectVLSIen_US
dc.subjectVLSI 2019en_US
dc.subject19MECen_US
dc.subject19MECVen_US
dc.subject19MECV02en_US
dc.titlePerformance Analysis of Arm Cortex-R Series Processorsen_US
dc.typeDissertationen_US
Appears in Collections:Dissertation, EC (VLSI)

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