Scan Construction and Validation of Channel and Rectilinear Designs

Abstract

to Moore’s law number of transistors placed in an integrated circuit (IC) or chip doubles approximately every two years hence chances of occurring defect is also increasing. The technology is scaling day by day. There are other reasons also which is leading to the presence of defect, error and fault in the design. Hence various strategies are applied to detect such defects and make our design error free. Design for test is one of the technique in which we add extra hardware to the design. This extra hardware added provide the controllability and observability points in the circuit. The main objective of adding this extra hardware to our design is to convert difficult to test sequential circuit into easy to test combinational circuit. Hence the testing of the circuit becomes easier. Random patterns are made to target the faulty sites, if the pattern is successful in targeting the fault then it saved else more patterns are generated to target the faults. Inserting DFT in complex design is not easy. Hence, we need to divide the large design into partitions or small block so that we can analyze each block individual. The goal here is to make design power and area aware by adding some extra circuitry. In this project of Scan construction and Validation of channel and rectilinear designs, a multi scan controller unit design flow was developed by our team to provide a solution for a long elongated channel designs. Sometimes it becomes difficult to have only a single controller for the single partition as the blocks present inside the design becomes too much congested which arises many issues such as the long wire routing and timing degradation. For example, if a design is having 20 partitions and 20 scan controllers. That means one controller for each partition but if the design is having an elongated partition then it can cause a problem due to congestion and timing degradation. Therefore we used a divide and conquer approach, means multiple scan controllers for a single partition. It helped us to overcome the timing degradation issues which occurred due to the long routing area. As a part of the project a role was given to me to develop and validate the netlist checkers for the multi Scan controller unit design flow. In this project the validation rules for multi Scan controller design unit based flow were developed.