Study and Analysis of Library Validation and Flow Methodology

Abstract

In PDK kits libraries plays most important role in whole IC circuit Design. With the help of libraries, the design times can be reduced to very short time. If Design and Validation done properly of PDK libraries, At Fabrication stage it is very easy to do fabrication of whole IC circuit design very easily and very rapidly. Designers just have to drag and drop cells from Libraries in their design for their logics. Without PDK libraries, Designers has to do design cells every time with their own so it will too much time consuming. So, to develop Libraries and to do validation of it is very vital task.

For doing PDK Libraries validation various files required for doing library validation on it. Files like config files, SPICE netlist files, LEF files, Verilog files, CDL files and GDS files are required for it. Once input files are ready, we can start doing validation on these PDK libraries.

PDK Library Validation has around 100+ testcases in each of the libraries and we have to do validation on these testcases before handing it to customers. This testcase validation can be done with the help of regression tool. It will testcases validation of all 100 at same time. Tests like DRC checks, LVS checks, Density checks, PVT simulation checks, Parasitic Extraction checks is done on these libraries. Regression tool will also give summary results of these testcases whether it is passing or failing testcases. Based on failed testcase we can do disposition on these testcases and must qualify them.