Analysis and Optimization of the Dynamic Power for NoC IP

Abstract

Power reduction is the key parameter to be controlled along with the area and noise in VLSI designs. The emerging demand for portable devices has met the area requirement. But still, these devices have not caught up with the power constraint. The requirement of high speed and high frequency of operations directly results in high clock frequencies. Thus, power becomes the key parameter to be considered while designing. Immediately at the RTL level of design, this parameter is given importance. The main component of power dissipation that can be controlled at the RTL level is the dynamic power.

This paper focuses on the analysis, the techniques, and the Power Artist tool used to reduce the dynamic power dissipation of NoC (Network on Chip) IPs at the RTL level. The main aim of the project is to use the clock gating techniques and insert the clock gating cells to reduce the unnecessary switching of the signals and thereby reduce the dynamic power. The Power Artist tool is used to help in the estimation and analysis of the power at this early stage of designing. Based on the reports generated by the tool and the GUI of the tool analysis is done. Based on the analysis, the RTL design is revised. This project introduces advanced methods for dealing with power estimation, analysis, and optimization during the early stages of the design process at the RTL level.

The Power Artist tool provides the complete RTL Design-For-Power (DFP) environment. The reports generated has detailed information about the power consumed by each block of the NOC IP design. It also gives the estimation of clock gating efficiency. All the results of the reports, analysis, RTL modifications, and power-saving reports are presented in this paper. Substantial power-saving is achieved using the Power Artist tool.