Design and Implementation of a Low-noise Low-power Bio-potential Amplifier For Biomedical Applications

Abstract

The continuous real-time monitoring of diverse physical parameters using bio-signals like ECG and EEG requires the bio-medical sensors for capturing those signals. Such a sensor consists of an analog front-end unit for which the operational transconductance amplifier (OTA) is an essential block. Along with noise and power, the parameters like CMRR, input impedance, DC offset and output ripple must be taken into consideration while designing as they equally affect the overall performance of amplifier.

In this work, the novel chopper-stabilized bio-potential amplifier is proposed. The chopper-stabilization method is used, by judiciously selected chopping frequency, to reduce the DC electrode offset and flicker noise. Further, the operational transconductance amplifier (OTA) is equipped with a additional circuit in form of forward path to enhance the input impedance without consuming extra power. In addition to this, the ripple reduction technique is employed at the output branch of the operational transconductance amplifier. The designed amplifier can be used for various applications like portable devices, wearable electronics and health care devices

The major challenge while designing was to maintain the balance in performance in terms of noise and power due to the existence of a trade-off between them. The specifications have been carefully chosen after detailed study of ECG and EEG recording systems for the bio-potential amplifier as it processes very low amplitude and frequency bio-signals, not only that the Layout design was very crucial due to issues of matching of various devices as it also affects overall circuit performance

The designed amplifier consumes 5.5 µW power with the mid-band gain of 40 dB. The passband for the designed amplifier is 0.1 Hz to 1 KHz. The input impedance is likewise boosted with the proposed method up to 200 MΩ. The noise is 42 nV/√Hz with CMRR of 82 dB. All the pre- and post-layout simulations are carried out using 180nm technology node.