Multiplierless Tunable Architecture for Signal Processing Transforms

Abstract

Signal processing algorithms like Discrete Fourier Transform, Discrete Cosine Transform, and Fast Fourier Transform find various applications in the field of Image processing, Wireless communication, Robotics, and many others. It covers basically three operations viz. Multiply, Shift and Accumulate. Hence if the input data goes on rising as in cases where high resolution is required the amount of multiply operations also rises significantly. For example, the number of complex multiplication operations in case of Discrete Fourier Transform is N2, where N is the number of points. Latency becomes an important issue which needs to be addressed in today’s era as we, humans, thrive for the fastest systems with maximum resolution. Multiplierless techniques for this purpose has been always a research area as it helps in reduction of the later part. Multipliers bound to increase the latency especially in the algorithms which use complex multiplications, for instance to evaluate a single complex multiplications minimum four real multiplications are required. Hence, in techniques where number of such complex multiplications need to be evaluated, latency increases to an exponential amount as in case of Discrete Fourier transform. To reduce latency we need to either emphasize on reduction in amount of data to be processed or change the processing structure which can affect the overall time to output. There are three broad techniques found in the literature for addressing this issue. Complex Multiplication techniques itself requires four real multiplication and two adders and hence it becomes practically infeasible for the case where large amount of data needs to be transformed. Coordinate rotation of digital computer (CORDIC) (Volder) based techniques are well known for the Multiplierless implementation of the sinusoids. However it carries certain drawbacks viz. large number of iterations and accuracy. This thesis addresses the issues of Multiplierless implementation of the rotation for two different cases viz. CORDIC based techniques and Coefficient combined selection and Shift and Add implementation (CCSSI) (Garrido, Qureshi, and Gustafsson). It proposes improvement to the existing CORDIC based approach as well as CCSSI. Platform used for the implementation of the proposed approach is MATLAB. At the end the work presents a tunable multiplier less architecture for implementation of sinusoidal as well as non-sinusoidal transforms. The thesis provides two different contributions in the field. 1) It proposes an efficient approach for the implementation of the Mixed Scaling and Rotation CORDIC (Lin and Wu) algorithm and also improves its SQNR by weighted amplifying factors. 2) The second contribution provides Coefficient combined & shift and add implementation (CCSSI) (Garrido, Qureshi, and Gustafsson) based approach to design Multiplierless rotators for various sinusoidal as well as non-sinusoidal transforms adding case of multiple constant rotators also. A novel tunable Combined co-efficient scaling and shift and add approach is proposed which takes into the following parameters. - Number of bits, - Number of adders, - Maximum allowable error - Number of points. The approach improves the range of coefficients with respect to number of adders (the range taken is from 2 to 10 adders), and number of bits (the range taken is from 1 to 64 bits), compared to the existing approaches and is shown in the results in Table 4.16. It also presents the Multiplierless architecture for the tunable parameter shown above.