Low Power Verification using Power Management Cells

Abstract

The last many years in power management have become the major problem when it comes to lower node technology, where static power dissipation is more than dynamic power dissipation. The low power verification tool uses a multi-voltage, low power static verification rule checker which will check the functionality and verify the low power architecture design perfectly and check whether any electrical violation is found or not. Low power standard IEEE 1801 is also known as Unified Power Format (UPF). It needs to verify its functionality and behaviourally correctness which ensures that it follows IEEE 1801 low power standards. UPF specifies all power intent information in the design flow. Using UPF commands power management can be controlled by specific cells like isolation, retention, power switches, and level-shifter cells which can be checked by a low power verification tool. The Low Power Verification tool normally checks and verifies any missing cells in the design and their connections with each other and finally, it will debug the issues.