Scan, ATPG analysis, Spyglass and Debug

Abstract

As the technology node reduces, the device becomes faster, and the complexity of the chip increases. The reduction in feature size increases the probability of manufacturing defects in an Integrated Circuit. Thus, it is significant to test the IC once they are taped out. To address the testing challenges for the physical defects, DFT (Design for Test) architecture has become popular in the industry in the recent times. Design for test is one of the techniques in which we add extra hardware to the design. This extra hardware added provide the controllability and observability points in the circuit. The main objective of adding this extra hardware to our design is to convert difficult to test sequential circuit into easy to test combinational circuit. Hence the testing of the circuit becomes easier. Random patterns are made to target the faulty sites, if the pattern is successful in targeting the fault, then it saved else more patterns are generated to target the faults. This project discusses the Scan, ATPG analysis and debug. It also includes spyglass DFTDSM for various partition/blocks. It majorly covers creating the ATPG environment for running multiple scan partitions at block level. It covers necessary reports generation and log file generations which is helpful for making coverage analysis and debug. Python script is developed to fetch total faults data, ATPG status, and simulation status by using coverage statistics reports and available log files for different blocks. It includes analyze and understand block level run & ATPG QoR(Quality of Result) for various partitions.