Enhancement of Test Driver for Modular Approach in Irem Glx Flow for Dynamic Analysis

Abstract

The tape-out stage marks the final phase of the physical design process and brings a sense of relief to the entire project team. It involves sending a clean layout file, typically in the form of GDS/OASIS format, to the foundry for fabrication, after successfully passing all the checks specified by the foundry. However, leading up to the tape-out, there are often numerous sleepless nights endured by physical design engineers and signoff engineers, as they work tirelessly to finalize the design. In VLSI design flow (for ASIC/SOC), Tape-out is the finishing process which completes the design and the database containing all the design information is send to the foundry for manufacturing. Unlike software product release (which can be easily patched in case a bug is discovered later), a design data base that is released for manufacturing cannot be patched once the wafer/chip are made. It would need to go through the whole process again. Also each revision of this tape-out process involves a very high cost and several months of lost time. This is why something like sign off process is used as a go ahead for tape-out This is nothing but a checklist to make sure if all the stages in the design process are completed and the data base is really ready to go for manufacturing. In my Project work, I Performed the steps carried out to observe the static/Dynamic IR and Signal/Power EM. From This I can conclude the result of power analysis and we can also optimize the design. Using RHSC Analysis, we can develop a test driver for Modular Approach in irem GLx Subflow.